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Host Interface (HI08)
6
The host interface (HI08) is a byte-wide, full-duplex, double-buffered parallel port that can
connect directly to the data bus of a host processor. The HI08 supports a variety of buses and
provides glueless connection with a number of industry-standard microcomputers,
microprocessors, and DSPs. The HI08 signals not used to interface to the host can be configured
as GPIO signals, up to a total of 16.
6.1 Features
The HI08 host is a slave device that operates asynchronously to the DSP core and host clocks.
Thus, the HI08 peripheral has a host processor interface and a DSP core interface. This section
lists the features of the host processor and DSP core interfaces.
6.1.1 DSP Core Interface
Mapping: Registers are directly mapped into eight internal X data memory locations.
Data word: DSP56311 24-bit (native) data words are supported, as are 8-bit and 16-bit
words.
Handshaking protocols:
— Software polled
— Interrupt driven
— Core DMA accesses
Instructions:
— Memory-mapped registers allow the standard MOVE instruction to transfer data
between the DSP56311 and external hosts.
— A special MOVEP instruction for I/O service capability using fast interrupts.
— Bit addressing instructions (for example, BCHG, BCLR, BSET, BTST, JCLR, JSCLR,
JSET, JSSET) simplify I/O service routines.
6.1.2 Host Processor Interface
Sixteen signals support non-multiplexed or multiplexed buses:
— H[0–7] / HAD[0–7] host data bus ( H[0–7] ) or host multiplexed address/data bus ( HAD[0–7] )
— HAS / HA0 address strobe ( HAS ) or host address line ( HA0 )
— HA8 / HA1 host address line ( HA8 ) or host address line ( HA1 )
— HA9 / HA2 host address line ( HA9 ) or host address line ( HA2 )
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
6-1
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